Here is a quick tutorial to demonstrate how to create a new Quartus II HDL project, compile it, then download it to your device.

Before we start there are a couple of prerequisites you’ll have to take care of first if you wish to follow along.

• Obviously, you will need to get your hands on a Cyclone II. If you’ve been reading some of my other blog posts you’ll know I’m using this setup. Your results will vary with different setups.
• Download and install Quartus II FPGA design software here. The Web Edition is $free. (The main drawback is the free edition only works with Windows). Feature Comparison
• If you’ve never worked with an FPGA, or any HDL language, go start working your way through the Altera training courses. They have an entire curriculum with all the information you’ll need to know to work with the Quartus II software. Once you get about 50% through the The Quartus II Software Design Series: Foundation class (and its “prerequisite” classes), then you’ll understand pretty much everything in this post.

(As a heads up, take the Verilog course instead of the VHDL one, since that is what I’ll be using )

Quick disclaimer: the following directions are based on using Quartus II 9.1sp1 software.

Okay, to start off, lets open Quartus II and create the software for our “Hello World” demo. Next, we’ll setup our hardware, and then download the configuration file.

The project we will be creating is the same shown in my previous demo. Essentially we’ll divide down our input clock, which is running at 48MHz, to something like 1Hz. We’ll connect a multimeter to the FPGA’s output and watch it toggle between High (3.3V) and Low (0V). I know it’s not the most exciting project, but sometimes you have to Shave a Yak before you can make something awesome.

Software Setup:

1. Open Quartus II, and create a new project. (File > New Project Wizard...)

2. Enter the path and name information for your project, and click Next:

3. Skip the Add Files [page 2 of 5] step, we’ll create our own files in a few steps.

4. Select the device we are targeting, we are using the EP2C8Q208C8, and click Finish (we’ll also skip the “EDA Tools and Settings” setup page):

5. Now you should have something like the following:

6. Quartus requires there to be some top level file for which your entire project is derived from. I prefer to use a Schematic document as the top level, this serves as a nice block level overview of the project and its contents. Plus I feel it is a lot easier to connect the wires an buses between the blocks and I/O pins.

So create a new Block Diagram/Schematic File. (File > New)

Now you’ll have an open document called Block1.bdf. Were not going to play with this document quite yet, so go ahead and save it to disk. We’ll come back to it in a little while. (File > Save As...). I recommend saving it with the same name as you chose in step 2. This will automatically select it as the top level file for your project.

If you save it with a different name, you will need to assign it as the project’s top level document by clicking the Files tab in the Project Navigator, then right-click on your Schematic file and click Set as Top-Level Entity, like so:

7. Now we need to add some meat and potato to this project, lets write some HDL to divide down the input clock (48MHz) down to something we can actually observe with our eyes (~1Hz).

Create a new Verilog file (File > New... > Verilog HDL File), and save it as SlowClock.v (File > Save As...)

8. Copy and paste the following code into your newly created SlockClock.v file:
SlowClock.v

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//Generate a very slow clock from the 24MHz input clock
module SlowClock(clock_in,clock_out,hi_out);
	//Input Ports
	input clock_in;
 
	//Output Ports
	output clock_out;
	output hi_out;
	//Port Definitions
	wire clock_out;
	wire hi_out;
 
	reg [26:0] counter; //Clock Divider
 
	//Set the output pin to the MSb of the counter.
 
	assign clock_out = counter[26]; 
	assign hi_out = 1'b1;
	//Essentially the counter counts up to 2^27, 
	//	then clock_out flips polarity	
	always @ (posedge clock_in) begin 
		counter <=  counter + 1;
	end
 
 
 
 
endmodule // End of Module counter

Now you should have something like this:

9. Okay, now that we created the SlowClock.v code, we will need to generate a Symbol File from the code, so that we can drop it into our top-level Schematic

In the Project Navigator, click the Files tab. Then Right-Click the SlowClock.v file, and click on the Create Symbol Files for Current File. Quartus will churn through the Verilog file for awhile and return a message box indicating success, or a failure if there was an error during symbol creation.

10. Now that the symbol file has been created let’s drop it into the top-level schematic. Re-Open the Hello_World.bdf file. Right-Click anywhere on the schematic and click (Insert > Symbol...). Open the Project folder and highlight the SlowClock item, then click OK. Then in the schematic file, click anywhere to place the SlowClock block:

You should have something like this:

11a. Next we need to place some I/O pins into the schematic. Again right click on the schematic and click (Insert > Symbol...). Navigate to the (primitives > pin) and select and place an input pin:

11b. Repeat step 11 but place an output pin, you should now have something like the following:

12. Next we need to connect the pins to the block. When you put your mouse next to the pin or block, the mouse will change to the node tool.

Connect the input pin to the clock_in, and the output pin to the clock_out.

13. Double click on the “pin_name” and “pin_name1” in order to rename them to something more useful. Try clk, and clk_out:

14. Now that we have the pins placed, we need to assign those pins to actual physical pins on the hardware (on the Cyclone II FPGA). The tool for this is the Pin Planner. But before we use that tool, we need to tell Quartus to analyze the files in order to make our input/output pins we placed available in said Pin Planner tool.

Click on the Start Analysis & Synthesis tool in the toolbar:

Quartus will churn for awhile, then report it’s success or failure.

15. Next, open the Pin Planner tool. (Assignments > Pins...):

16a. For the clk node, double click the Location text box, and assign it to Pin 77:

16b. Next, set the clk_out node to Pin_59:

17. One last step left for the software setup. Close out of the Pin Planner. Now we can do a Full Compile of the project to generate the configuration file. The configuration file is what we download to the FPGA.

Click the Start Compilation button in the toolbar:

Quartus should grind for awhile and eventually give a popup declaring success.

Hardware Setup:

18. Connect the 48MHz clock to Pin 77.

19. Connect your multimeter to Pin 59.

20. Connect your Altera Programmer to the FPGA breakout board’s JTAG port, then connect it to your computers parallel port.

21. Turn the power on. (3.3V VCCIO, 1.2V VCCINT)

Easy as that, now we can download the configuration file and were done.

Programming the Cyclone II:

22. Back in the Quartus II software, run the Programming tool (Tools > Programmer).

23. Make sure you are configured to use the ByteBlaster configuration hardware.

(I ran into some problems with this step. Turns out my Parallel port was disabled in the Bios. Once I enabled the port in the Bios, I had to uninstall and re-install the Parallel port in my Windows Device Manager.

24. Click the Start button to download the configuration file to hardware.

You should now have project running and hopefully it looks like this:

(If it does, feel free to give off an evil-mad scientist laugh at this point. Good work!).

Hopefully that helps you get up and running with the Cyclone II FPGA. Feel free to leave some feedback in the comments section about how this process went for you. Let me know if you run into any problems along the way. Good Luck!!

I threw together a quick demo to prove to myself that my FPGA was powered and working. It was important that the demonstration used some form of sequential logic, so that I could be sure the clock was alive and running as well.

The ideal quick and easy first project would be to just output the clock signal into a pin and drive an LED. Unfortunately, my eyeballs can’t register a 24MHz signal and I didn’t want to waste time messing around with an LED. (It’s important to ensure we don’t over draw current from the FPGA’s logic pins, so directly driving an LED, even with a current limiting resistor, is not a great idea).

I ended up with the slightly less exciting compromise of using a counter to divide the clock down to ~1Hz, and a multimeter to display that the logic level is changing. Exciting? Not so much, but suitable for a nice “Hello World” program. Besides, I picked up a Serial Enabled LCD display for the next demo, and then I’ll be able to actually display “Hello World”, that should be slightly more flashy

And now for the demo… Watch the multimeter switch from a High Logic Level (~3.3V), to a low logic level (~0V):

Here is a look at the Verilog HDL source code driving this demo:
SlowClock.v

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//Generate a very slow clock from the 24MHz input clock
module SlowClock(clock_in,clock_out);
	//Input Ports
	input clock_in;
 
	//Output Ports
	output clock_out;
 
	//Port Definitions
	wire clock_out;
 
 
	reg [26:0] counter; //Clock Divider
 
	//Set the output pin to the MSb of the counter.
	assign clock_out = counter[26]; 
 
	//Essentially the counter counts up to 2^27, 
	//	then clock_out flips polarity	
	always @ (posedge clock_in) begin 
		counter <=  counter + 1;
	end
 
endmodule // End of Module counter

There is a lot more details on how to go about setting up the code, getting it compiled, assigning the pins and finally programing the FPGA. Upcoming blog posts will cover all those juicy details. Also, I’ll put together the full Bill of Materials (BOM) that I promised previously.

I decided to interrupt my Cyclone II Handbook dissection series in order to build the voltage regulators needed for the Saturn Project.

The EP2C8 Cyclone II FPGA we have on our breakout board requires nine voltage supplies:

From the Cyclone® II EP2C8 & EP2C8A Device Pin-Out document

Fortunately we can minimize the overall number of voltage regulators required by using a single regulator for the 1.2V supplies, and another regulator for the I/O supplies. I have some concern about noise coupling between the different analog and digital supplies, though our breakout board does have some decoupling capacitors. I’m thinking this should be adequate for our prototyping setup.

Breakout Board Voltage Supplies Schematic

For future reference, the Altera Cyclone II Handbook has some guidelines for isolating the PLL power supplies at the PCB level:

Isolate the power connected to VCCA from the power to the rest of the Cyclone II device or any other digital device on the board. You can use one of three different methods of isolating the VCCA pin:

• Use separate VCCA power planes
• Use a partitioned VCCA island within the VCCINT plane
• Use thick VCCA traces

I decided to pick up a SMPS wall-wart to step down and rectify the mains (120VAC) to 9VDC. The clock I picked out happens to need a 5V supply, so the 9V wall-wart is then connected to a 5V Breadboard power supply from SparkFun. (Plus, having a 5V rail will no doubt come in handy some day).

After selecting the components mentioned above, I moved on to select two linear regulators to supply the 1.2V and 3.3V, both of which are powered from the 5V Breadboard Power Supply. My main design goal for these regulators was to minimize the component count for simplicity sake. Have a look at the schematic below, and you can see I only needed 4 caps and a resistor.

Saturn Project - Regulator Schematic

I used a LT1084-3.3, and a LT3080.

The 1.2V regulator can draw up to 1.1A, and it doesn’t require a heat sink (Although, I might add one depending on how hot it gets). It has less than 1mV load regulation and <0.001%/V line regulation. One important thing to note is that this regulator has a minimum of 500uA output current required for proper operation. If you don’t meet this constraint, the output will swing to ~3.3V and possibly damage the FPGA. For the time being I decided to stick a 1kohm resistor on the output to sink 1.2mA just to be safe. Since I’m still in the prototyping phase I can’t be certain of the regulator start-up sequence, or what the quiescent current consumption of the VCCINT rail will be.

There isn’t anything too exciting about the 3.3V regulator, Linear Technology claims “higher efficiency” than other products on the market. It can supply up to 5A, which should be more than enough juice to power our FPGA and other fun circuits down the line.

Using LTSpice (a free, awesome, circuit simulator tool), I put together the schematic shown above, and I’ve made it available for download. I recommend playing around with it, try removing the load on the 1.2V regulator and watch what happens to the output. You will probably need to “install” the LM317 spice model which I’ve included (check out the readme.txt file for instructions).

Download the LTSpice Power Supply Schematic:

SaturnProject – Power Supply Schematic
(SaturnProject_PowerSupply.zip)
Includes the LM317 SPICE model.

Now that we’ve covered all the details, let’s get some satisfaction and check out the regulators in action!

Once I get to the point where I put together a custom PCBA, I’m sure I will revisit the regulator design and put together a more robust solution with surface mount components. Including some circuits to protect against over/under voltage situations, spikes, and accidental shorts, but in the mean time… we’re in business!

Next week I’ll show you the system clock I selected, and return to my handbook dissection and see what it takes to download a configuration file to the Cyclone II and start putting it to work. I’ll also put together a full bill of materials (BOM) so you can pick up all the components I’ve been talking about.

Another note for future reference…. Each of the CII supplies use more than one pin, here is a list of the those pins (so I don’t try to use them for I/O later and blow up the FPGA )

• VCCINT – Pin 32, 66, 79, 120, 178, 190,
• VCCIO1 – Pin 7, 29, 42
• VCCIO2 – Pin 166, 172, 183, 194, 202
• VCCIO3 – Pin 109, 122, 136, 148
• VCCIO4 – Pin 62, 71, 83, 91, 98
• VCCA_PLL1 – Pin 53, (54 – GND_A)
• VCCD_PLL1 – Pin 51, (50, 52 – GND_D)
• VCCA_PLL2 – Pin 157, (158 – GND_A)
• VCCD_PLL2 – Pin 155, (154, 156 – GND_D)

The Cyclone II Handbook, Volume 1 has 470 pages. There is a ton of great information in that document, but in an effort to make it more digestible, I’m going to try to break it apart and present some of the more vital information it contains.

The Handbook is a general guide to the full line of Cyclone II products, which come in a variety of “flavors”. Each with a confusing serial number to distinguish them from their siblings.

(For the sake of brevity I’m going to start referring to the Cyclone II, as the CII.)

Here is a breakdown of the different flavors we have. (I highlighted the particular CII that comes with our breakout board)

Not only are there different versions with different feature sets, but we also have different speed grades, and package selections:

You can see we have one of the smallest and slowest FPGAs available in the family, but at this point it will take us a long time to max out its capabilities. Probably the most important part for us to worry about is the package type, our 208 pin QPF package is manageable, albeit tedious, to hand solder. Once we start thinking about the larger Ball Grid Array (BGA) packages we will need to investigate different soldering techniques. (In fact, the reflow soldering method it really the way to go even with the QFP, so I’ll mark that down on my list of things to learn how to do.)

Back to the Handbook… The second section describes the overall architecture of the Cyclone II:

Cyclone® II devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between logic array blocks (LABs), embedded memory blocks, and embedded multipliers.

Here we have a high level block diagram of the core components of the CII:

Within the Logic Arrays are the Logic Elements (LEs), which are the basic building blocks for the core logic, the “atom” of the FPGA if you will.
Each Logic Element provides the following functionality:

• A four-input look-up table (LUT), which is a function generator that can implement any function of four variables
• A programmable register
• A carry chain connection
• A register chain connection
• The ability to drive all types of interconnects: local, row, column, register chain, and direct link interconnects
• Support for register packing
• Support for register feedback

Let’s have a look at the internal structure of the Logic Elements, but don’t worry we won’t even have to think about the internal workings of the LE, rest assured the software we will be using takes care of all the complexities, we just have to specify what Flip-Flops and Gates we want.

The CII comes with embedded memory and multiplier blocks. Each of the multiplier blocks allow us to create up to two 9 × 9-bit multipliers, or one 18 × 18-bit multiplier.

The memory blocks (M4K), are true dual port memories, meaning you can read and write at different addresses simultaneously if you want. Each block allows 4K + parity totaling 4,608 bits of memory. (Our particular CII contains 32 M4K blocks).

The next component of our FPGA is the I/O Elements (IOEs), which are actually quite complex. They support multiple different Input/Output standards, 3.3/2.5/1.8/1.5 TTL, differential I/O, and bunch of other standards I’ve never heard of. The IOEs have different advanced options like slew rate control, drive strength selection, programmable pull up resistors, bus-hold and open-drain output.

One of the coolest things about the IOEs is that they are grouped into four different banks (eight banks on the larger CIIs), and each bank can be powered by a separate supply voltage. This is great if you want to interface with one IC running at 3.3V and connect to another at 1.8V with no need for level-shifting hardware! Each bank has its own VCCIO pin for the appropriate supply voltage, while the core FPGA logic is driven by an additional VCCINT supply (1.2V).

All of these different components inside the FPGA are connected by a “fabric” of interconnections and routing assets, which are described in detail in the handbook. Fortunately for us, we can just allow the software to take care of all the signal routing.

That wraps up this week’s dissection. Tune in next week for Part 2, where we will take a look at the PLLs and the clock tree structure.

The blog is getting to the point where it’s ready to go. As the New Year rolls in I will get to work on updating the site more frequently. The first order of business is to start blogging about my Saturn Project.

Come back soon, until then, enjoy the Holidays!!