This is a tutorial to walk you through how to use Quartus II and ModelSim software together to create and analyze a simple design (an inverter), then we’ll compare the RTL and Gate-Level simulations with the results on a DE0-Nano.

This tutorial assumes you have some basic experience working with Quartus II. Going through the examples in the DE0-Nano User manual should be sufficient.

For the tutorial, I’m using the following versions of the software:

• Quartus II v. 11.0 Build 208
• ModelSim 10.0C (Quartus 11.1) Starter Edition

You can see the versions of my software aren’t the same, this is probably why I have the EDA tool pathing issue described below. I recommend installing both tools at the same time, from the same release.

Note that you will have to install the ModelSim (Altera Version) software separately from Quartus, Altera’s website makes it seem like they come bundled but this is not the case.

First Step – Create the Design

Start by creating a new project in Quartus II. When using the New Project Wizard, make sure to select the DE0-Nano’s FPGA which is the EP4CE22F17C6. Also, select the ModelSim-Altera as the simulation tool and select the format as Verilog HDL.

Create the Inverter HDL Code

Now create a new Verilog file, which you can save as SimpleInverter.v.

module SimpleInverter(
	input wire a,
	output wire a_bar
	);

	assign a_bar = ~a;

	endmodule

Now you need to set the Inverter as the TopLevel Entity

You’ll need to run the Analysis & Synthesis portion of the compilation process to prepare the files for ModelSim

RTL Level Simulation with ModelSim

Now that the HDL has been created we can start ModelSim (from within Quartus) to do the RTL verification and ensure the design works as we expect.

Start ModelSim using the menu: Tools -> Run EDA Simulation Tool -> EDA RTL Simulation

If you get an error message where the path to the ModelSim software is not specified, search your C:\altera folder for the vsim.exe file. Then update the path by using the Tools -> Path menu, next set the path in the EDA Tool Options category

It’s quite confusing the first time you use ModelSim from Quartus because after ModelSim opens it doesn’t give you any tips as to where your Inverter went. By default the Inverter is put into the “work” Library.

Once you find the module, double click it, or right click and start the simulation:

Now you should see something like this:

If you don’t see all these windows you can bring them up from the Windows -> Toolbar menu.

Create a Stimulus

First thing we need to do is to create a stimulus on our input (a), you can right click the a in the Objects window and for this example let’s just make it a clock:

Let’s make it a 20Mhz clock, so a period of 50nS, make sure to keep the lowercase “ns” or ModelSim will complain.

Next, we’ll add the two signals (a and a_bar) to the Wave window, there are a few different ways to do this, but I prefer to just shift-select both a and a_bar and drag-drop it into the Wave window:

Simulate some Time

Now we need to tell ModelSim to start simulating some portion of time, so lets click the Run button after adjusting the RunLength to 200nS:

Now you should see something like the following in the Wave window:

We need to re-zoom the Wave window to better see the simulation:

You can also change the “Radix” so the values will come up as binary and not “St1″ and “St0″, just shift-select both signals, right click and select Radix…

And select “Binary”:

Analyzing the signal

You can zoom in on the signal easily using the CTRL+Mousewheel. Now we can see that our design is working exactly as we expect an ideal inverter to work. There is no propagation delay between a going high and a_bar going low:

Simulating a Real-World Inverter (Gate-Level Simulation)

In order to see what a non-ideal inverter might look like, let’s jump back to Quartus.

Assign pins

Open the pin planner and assign the following pins:

Here is the location of the pins we chose:

Full Compilation

Now kick off a full compilation:

Gate Level Simulation

Now that the full compilation has finished, we can run gate level simulation. This will include some of the real-world delays and give us a better expectation of how the design will really work.

Using the Tools menu, start the gate level simulation:

Next, you’ll be asked which timing model you want to use, let’s just pick the default, “Slow -6 1.2V 85 Model”, this simulates nominal core voltage at 85degC.

If you get a NativeLink error, something like “error deleting "msim_transcript": permission denied.” you’ll need to make sure you close your current ModelSim environment, or at least stop the current simulation.

Kicking off the Gate-Level Simulation

Now comes a little trick to start this simulation. If you try to begin the gate-level simulation like we did with the RTL simulation (double clicking the work/SimpleInverter module), you’ll be given the following error:

# Loading work.SimpleInverter
# ** Error: (vsim-3033) SimpleInverter_6_1200mv_85c_slow.vo(67): Instantiation of 'cycloneive_io_obuf' failed. The design unit was not found.
#         Region: /SimpleInverter
#         Searched libraries:
#             C:\altera\11.0sp1\simulation\modelsim\gate_work
# ** Error: (vsim-3033) SimpleInverter_6_1200mv_85c_slow.vo(77): Instantiation of 'cycloneive_io_ibuf' failed. The design unit was not found.
#         Region: /SimpleInverter
#         Searched libraries:
#             C:\altera\11.0sp1\simulation\modelsim\gate_work
# Error loading design

We need to start the simulation and tell it where to find the Cyclone IVe I/O pin library.

We’ll click the Simulate -> Start Simulation... menu:

In the Design tab, enter the work.SimpleInverter as the Design unit:

Next we click the Library tab, and add the cycloneive_ver (“ver” for the verilog version of the Library). (Make sure you have the “e” after the “iv” otherwise your design will fail.)

After you kick off the simulation you’ll be presented with a similar ModelSim simulation as before, however there are now a few extra signals and design units. You can see the signals we care about, a and a_bar are still present.

Simulate

Let’s add those signals to the Wave window, create an input stimulus on the a signal and start a 200nS simulation like we did in the RTL Simulation above.

Analyzing the Results

Now we see a very different behavior than we saw in the RTL simulation, there is some propagation delay between a going high and a_bar going low.

Measuring Propagation Delay

You can add a second cursor to the wave window by clicking the “Insert Cursor” button:

We can see ModelSim and the Altera models are estimating a 6.7nS delay.

Verifying in Hardware

In order to verify the results given in ModelSim, I downloaded the configuration file to my DE0-Nano. Using a pulse generator and an oscilloscope I was able to collect the following data. (Data was pulled from the scope and regenerated in Python using matplotlib)

Zooming in a little closer, we can measure a propagation delay of about 6.5nS, quite close to the results given in the simulation. (My testing was done at ~30degC not the 85degC)

In this tutorial, we’ve covered the basics of running simulations in ModelSim of designs created in Quartus II. Let me know if this was useful and informative, or if I’ve left anything important out.

Further Reading:
MIT ModelSim Tutorial (Introductory Digital Systems Laboratory)

Usually, I would get a few people linking to Idle-Logic from SparkFun’s Cyclone II Breakout board product page. Looking through the logs recently I noticed that this trickle of referrals dried up. I went to investigate only to find that the board has been discontinued… sad times.

Down the road I plan on making my own breakout board, probably with the basic regulators and USB connections to make it run. I would try to keep it cheap and as barebones as possible, and my thought is to build custom “headers” similar to what is done on the Arduino.

Leave a message in the comments if you would be interested in such a product so I can set my motivation appropriately.

Using a similar technique I covered in my last post, reader Bryan Richmond has been able to successfully program an Altera Cyclone II using C++, libftdi and a FT2232H USB/UART.

From my understanding Bryan is running Debian on an ARM, and is programming the Cyclone II on his Morph-IC-II development board.

I haven’t had a chance to test the code, but Bryan has shown it to process and send a 50K RBF file in less than 3 seconds. The code demonstrates the usage of many libftdi function calls not mentioned in my last post. Also, Bryan’s code is checking the NCONF_DONE pin of the FPGA to ensure the configuration file has been sent correctly.

Great work Bryan!