July 12th, 2014|
Reader Paul Green was inspired by one of my blog posts, and has done an amazing job of taking it to the next level. The vj-uart project allows communication to the DE0-Nano using a virtual com port connection.
This tutorial will explain how to pull the files down from GitHub, and how to start talking […]
June 7th, 2014|
The blog has a new look! The original design was over 4 years old and was starting to look a little dated. It just felt like time to make a change. I still have plenty of things I need to tweak with the new look, but it’s ready to be pushed out. If I […]
April 5th, 2014|
This week the idle-logic blog crossed the 50K all time views mark:
From people all over the world:
It’s a humble number, but a satisfying milestone to cross.
New Blog Feature
I’ve been remiss to add new blog posts because I didn’t want to bury the particularly popular posts currently on the front page. In order to remedy […]
September 21st, 2013|
I created a small improvement to my Quartus b2vFixer.tcl script. You can find the original post describing the purpose of this script here. In summary, this script is used to convert a top-level Quartus BDF (Block Design File) to a Verilog file usable in ModelSim.
The only real change in this update is to allow […]
August 11th, 2013|Jesse, a professor at the The Hague University of Applied Sciences (Netherlands), has been kind enough to share with us his BDF to VHDL conversion script which can also kick off Modelsim.