The Cyclone II Handbook, Volume 1 has 470 pages. There is a ton of great information in that document, but in an effort to make it more digestible, I’m going to try to break it apart and present some of the more vital information it contains.
The Handbook is a general guide to the full line of Cyclone II products, which come in a variety of “flavors”. Each with a confusing serial number to distinguish them from their siblings.
(For the sake of brevity I’m going to start referring to the Cyclone II, as the CII.)
Here is a breakdown of the different flavors we have. (I highlighted the particular CII that comes with our breakout board)
Not only are there different versions with different feature sets, but we also have different speed grades, and package selections:
You can see we have one of the smallest and slowest FPGAs available in the family, but at this point it will take us a long time to max out its capabilities. Probably the most important part for us to worry about is the package type, our 208 pin QPF package is manageable, albeit tedious, to hand solder. Once we start thinking about the larger Ball Grid Array (BGA) packages we will need to investigate different soldering techniques. (In fact, the reflow soldering method it really the way to go even with the QFP, so I’ll mark that down on my list of things to learn how to do.)
Back to the Handbook… The second section describes the overall architecture of the Cyclone II:
Cyclone® II devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between logic array blocks (LABs), embedded memory blocks, and embedded multipliers.
Here we have a high level block diagram of the core components of the CII:
Within the Logic Arrays are the Logic Elements (LEs), which are the basic building blocks for the core logic, the “atom” of the FPGA if you will.
Each Logic Element provides the following functionality:
- A four-input look-up table (LUT), which is a function generator that can implement any function of four variables
- A programmable register
- A carry chain connection
- A register chain connection
- The ability to drive all types of interconnects: local, row, column, register chain, and direct link interconnects
- Support for register packing
- Support for register feedback
Let’s have a look at the internal structure of the Logic Elements, but don’t worry we won’t even have to think about the internal workings of the LE, rest assured the software we will be using takes care of all the complexities, we just have to specify what Flip-Flops and Gates we want.
The CII comes with embedded memory and multiplier blocks. Each of the multiplier blocks allow us to create up to two 9 × 9-bit multipliers, or one 18 × 18-bit multiplier.
The memory blocks (M4K), are true dual port memories, meaning you can read and write at different addresses simultaneously if you want. Each block allows 4K + parity totaling 4,608 bits of memory. (Our particular CII contains 32 M4K blocks).
The next component of our FPGA is the I/O Elements (IOEs), which are actually quite complex. They support multiple different Input/Output standards, 3.3/2.5/1.8/1.5 TTL, differential I/O, and bunch of other standards I’ve never heard of. The IOEs have different advanced options like slew rate control, drive strength selection, programmable pull up resistors, bus-hold and open-drain output.
One of the coolest things about the IOEs is that they are grouped into four different banks (eight banks on the larger CIIs), and each bank can be powered by a separate supply voltage. This is great if you want to interface with one IC running at 3.3V and connect to another at 1.8V with no need for level-shifting hardware! Each bank has its own
VCCIO pin for the appropriate supply voltage, while the core FPGA logic is driven by an additional
VCCINT supply (1.2V).
All of these different components inside the FPGA are connected by a “fabric” of interconnections and routing assets, which are described in detail in the handbook. Fortunately for us, we can just allow the software to take care of all the signal routing.
That wraps up this week’s dissection. Tune in next week for Part 2, where we will take a look at the PLLs and the clock tree structure.