Welcome back to the second part of the series dissecting the Altera Cyclone II Handbook. I’m ripping out all of the important information you need to know from the 470 page tome, and condensing it down to a couple of blog posts. This week I’m going to take a look at the clocks and PLL blocks.
One of the major problems you run into when designing sequential logic, is clock skew. Essentially you can have a situation where one clock signal is driving multiple Flip-Flops across the breadth of the IC, because of delays inherent to the routing circuits as well as the laws of physics, some delay (skew) can be introduced between the signals. You might think that two Flip-Flops are clocking in data at the exact same time, when in reality they are not. Check out the links I sprinkled into this paragraph for more details.
The Cyclone II (like most, if not all FPGAs) comes with dedicated global clock networks which give us a more even distribution of clock signals. This can help us to overcome the issues mentioned above, but it is important to note that while they help alleviate timing violations, they won’t completely eliminate the problem. It is up to the user to analyze the design, with the help of the software tools, to ensure it will be robust and hardened against these timing problems.
The global clock networks can be used not only for clocks, but also for asynchronous clears, presets, and clock enables signals. Each of the CII global clock networks has its own clock control block, which is in charge of multiplexing the selected clock onto the network (or disabling the clock, for power-saving modes).
The CII has both dedicated, and dual-purpose clock pins. Both of these types of clock pins can drive the global clock network, or be used for general purpose I/O. It is also possible to drive the global clock networks with internally generated signals (think reset or clear signals), or be driven by the PLLs.
Some of you might be wondering what in the heck are PLLs? A PLL or a phased-locked loop is, in general, a “control system that generates a signal that has a fixed relation to the phase of a ‘reference’ signal”. To be more specific to our FPGA, the PLL is a logic block that will take an input clock (or signal) that we provide to the circuit, and can manipulate it in order to obtain a new clock signal which is scaled or phase shifted.
For example, you could connect a 24 MHz clock to the FPGA, and have the PLL’s kick it up to a 48 MHz clock. Here is a table showing the CII PLL features, take note of the m and n scale range, this lets you know what clocks frequencies you can generate:
Well, that will about do it for this week. Check back next time, where I’ll go over how to generate the FPGA’s configuration (Quartus II) and show you what you need to know to download the configuration file into the FPGA.