As I alluded to in a previous post, I’ve come up with a way to program my Altera Cyclone II FPGA with a $15 FT232RL USB to UART Bridge, avoiding the $300 investment in one of Altera’s USB-Blaster cables.

I’m going to break this tutorial up into three separate posts. The first has already been uploaded: libFTDI v0.18 with Ubuntu (Lucid Lynx), which describes how to install the proper version of the hardware drivers on Ubuntu. This post, being the second in the series, will cover the hardware modifications required to interface the FT232RL with an FPGA setup. The third post will show the Python code used to push the FPGA configuration file down to the FPGA bit by bit.

The Cyclone II FPGA has a few different methods for configuration as described by the Altera Cyclone II Handbook:

  1. Active serial (AS) : Configuration using serial configuration devices (EPCS1, EPCS4, EPCS16 or EPCS64 devices). These can be described as basically non-volatile memory blocks that hold your configuration file. The Cyclone II will actually access this memory to configure itself on power-up.
  2. Passive serial (PS) : Configuration using enhanced configuration devices (EPC4, EPC8, and EPC16 devices), EPC2 and EPC1 configuration devices, an intelligent host (microprocessor), or a download cable.
  3. JTAG-based configuration : Configuration via JTAG pins using a download cable, an intelligent host (microprocessor), or the JamTM Standard Test and Programming Language (STAPL)

Previously, I had been configuring the Cyclone II on my SparkFun breakout board using the JTAG configuration method. Now I decided I wanted to start using a USB connection instead of the antiquated parallel port required for the Altera JTAG programmer, but to be honest this decision was partially based on the fact that my new computer has no parallel port. 😉

For this USB programming solution, we will be using the Passive Serial (PS) configuration method where our computer will act as the intelligent host.

The following diagram shows how we need to configure the breakoutboard for Passive Serial:

Here is the breakout board schematic showing the modifications we need to make: Removing four solder jumpers, and connecting half of one jumper to the supply voltage (Original Schematic here):

And here is the breakout board layout showing the changes to be made:

Finally, here is a picture of the changes made on my breakout board:

Okay, now we need to connect the FT232RL Breakout-board (BOB) to our Cyclone II BOB. First, let me show you the schematic for the FT232RL Breakout Board:

We are going to be using the FT232RL in bitbang mode. According to Table 2.1 of the FT232R Bit Bang Mode’s application note we have the following pin-outs for bitbang mode:

Bit Bang Pin Chip Pins Name
0 1 TXD
1 5 RXD
2 3 RTS
3 11 CTS
4 2 DTR
5 9 DSR
6 10 DCD
7 6 RI

For convenience, I’ve drawn out where the bitbang pins are on the breakoutboard:

Now, our final step in setting up the hardware is to connect the DATA0, DCLK and NCONFIG pins of the Cyclone II to the FT232RL breakout board:

  1. Connect Pin 20 (DATA0) of the Cyclone II BOB to the BitBang Pin 0 of the FT232RL.
  2. Connect Pin 21 (DCLK) to BitBang Pin 1.
  3. Connect Pin 26 (NCONFIG) to Bitbang Pin 2.
    • Here is a capture from the Cyclone II BOB Schematic:

      Finally, here is a picture of my FT232RL BOB inserted into my protoboard, you can see I ran some wires from the eight BitBang lines to the side of the protoboard for easier access.

      That concludes the hardware modifications required for programming the Cyclone II (on a SparkFun BOB) using the FT232RL. Next post I’ll show the software required to process a configuration file and send it to the Cyclone II, bit by bit.

      (Teaser: I’m currently working on a MUX system that will allow us to “reconnect” those FT232RL pins to I/O pins of the Cyclone II, instead of always being connected to the FPGA’s config pins. With a little work it should give us the ability to program and communicate with the FPGA for less than $15! 🙂 )