Programming the Cyclone II using C++, libftdi and a FT2232H

Using a similar technique I covered in my last post, reader Bryan Richmond has been able to successfully program an Altera Cyclone II using C++, libftdi and a FT2232H USB/UART.

From my understanding Bryan is running Debian on an ARM, and is programming the Cyclone II on his Morph-IC-II development board.

I haven’t had a chance to test the code, but Bryan has shown it to process and send a 50K RBF file in less than 3 seconds. The code demonstrates the usage of many libftdi function calls not mentioned in my last post. Also, Bryan’s code is checking the NCONF_DONE pin of the FPGA to ensure the configuration file has been sent correctly.

Great work Bryan!

You can download the C++ file here:

Download
passiveSerial.zip

Contains:

  • passiveSerial.cpp
2011
03/22
CATEGORY
Altera
Cyclone II
TAGS






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    • td
    • June 23rd, 2011 11:03 pm MDT

    I need to get me some of these FDTI chip and try the https://www.ohloh.net/p/python-ftdi module for SPI and I2C.

  2. Interesting, I’ve never heard of this python user space driver. I’m not using one of the devices they support, but would be neat to check out. Let me know how it works if you do try it out.

    • russdx
    • December 14th, 2011 3:34 am MDT

    50k in 3seconds seams VERY slow for this ftdi chip, i thought it was ment to support up to 12mbs?

  4. Hi Russel, I’m not positive the max throughput for this IC, but I assume that it is quoted for UART mode of operation. Traditionally bit-banging is much slower, and I’m not sure if the drivers are optimized to maximize throughput in this mode.

    • russdx
    • December 15th, 2011 3:06 am MDT

    ah, thats very interesting i plan to use this exact chip for one of my projects and i need upto 100k a sec at least, my plan was to use bit bang mode with a nice 8bit bus from the ftdi chip.

    but if this is all it can do, i think ill just go down the normal uart route hehe :)

      • Bryan Richmond
      • February 7th, 2012 1:15 pm MDT

      hey..so that 3 seconds is just on some prototype code. I can program them in less that a second now, haven’t really clocked it officially.
      I did however did do some communication speed tests. Configuring the ftdi chip and fpga for synchronous fifo mode heres what I got

      Upload Test: 140Mb/s (from FPGA to PC)
      Download Test: 120Mb/s (from PC to FPGA)
      Echo Test: 100Mb/s

      for asynchronous fifo mode:
      Upload Test: 28.89Mb/s
      Download Test: 59.52Mb/s
      Echo Test: 23Mb/s

      That’s mega bits

    • Nice, thanks for the follow up Bryan!

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