How to communicate between a PC and a design running on the DE0-Nano using the Virtual JTAG Megafunction, a Tcl TCP/IP Server running in quartus_stp with virtually any programming language.
*07/05/14 – Reader Paul Green has extended this post’s idea and built a virtual com port for talking to the DE0-Nano. Check out his very well written vj-uart project on GitHub. Here is my tutorial on how to use vj-uart.
*04/18/14 – See the comments below for the new open_sld project from Vern Muhr which allows direct access to the Virtual JTAG interface (using Python) without the TCP/IP TCL pipe described in this article.
The first thing I wondered when I got my hands on the DE0-Nano was how best to communicate with a design inside the FPGA. Initially, I assumed that with the USB connection onboard there would be some form of UART connected to a few of the FGPA Pins. Unfortunately, this was not the case.
I sent an email to the creators of the DE0-Nano, terasIC asking how best to go about communicating with a design and their application engineer recommended adding a second USB connection with something like the FTDI 232RL USB to UART Bridge.
I was still convinced there had to be a more elegant way. Fortunately, I came across this post on the Altera forums talking about the Virtual JTAG interface. Thanks to those pointers from the ever helpful Dave, the seed was planted for the solution presented below.
Virtual JTAG Example – Blinky Lights
To demonstrate this functionality I put together a project that uses the DE0-Nano LEDs to count from 0 to 128 in binary, all at the command of a Python script. Nothing better than some flashing lights to demonstrate a new technique.
Download the Project Files
Here I’m attaching the project files, then below I’ll discuss how everything works. I’ve uploaded the files as an Archived Quartus Project (inside a ZIP file since WordPress doesn’t like .qar file types), this contains all of the Quartus Design Files (in Verilog), the Tcl Server Script and the Python File. Let me know in the comments if you would prefer the raw files outside a QAR file instead. (Or both?)
Digital Design Files (Quartus Project)
I’m just going to provide a quick overview of the design and not go into a step by step guide for how to recreate the project from scratch. Have a look at the two examples in the DE0-Nano User Manual for very good instructions on how to create a project from start to finish.
Top Level
My preference is to use schematic entry for the top level design, I think this makes it easier to understand the overall functionality:
vJTAG
The first block is the vJTAG, which is a sld_virtual_jtag
instance generated by the Altera Megafunction Wizard.
The Megafunction User Guide has a great description for what this block is all about:
The virtual JTAG megafunction IP gives you direct access to the JTAG control signals routed to the FPGA core logic, which gives you a fine granularity of control over the JTAG resource. This opens up the JTAG resource as a general-purpose serial communication interface. A complete Tcl API is available for sending and receiving transactions into your device during runtime. Because the JTAG pins are readily accessible during runtime, this megafunction can be an easy way to customize a JTAG scan chain internal to the device, which can be used to create debugging applications.
vJTAG_interface
This is the block with all the brains for capturing and sending data through the vJTAG. There are two main pieces of information that come from the PC to the Virtual JTAG, an instruction register and a data register. Essentially, we are required to capture bit shifted data from the tdi
pin while shifting out data back to the interface through the tdo pin. The ir_in
output tells us what specific instruction is being requested.
In this case we configured the vJTAG to have a 1 bit wide instruction register (0 = Bypass, 1 = Capture New LED Output Settings).
Here is the verilog code for this block:
module vJTAG_interface (
input tck, tdi, aclr, ir_in,v_sdr, udr,
output reg [6:0] LEDs,
output reg tdo
);
reg DR0_bypass_reg; // Safeguard in case bad IR is sent through JTAG
reg [6:0] DR1; // Date, time and revision DR. We could make separate Data Registers for each one, but
wire select_DR0 = !ir_in; // Default to 0, which is the bypass register
wire select_DR1 = ir_in; //Data Register 1 will collect the new LED Settings
always @ (posedge tck or posedge aclr)
begin
if (aclr)
begin
DR0_bypass_reg <= 1’b0;
DR1 <= 7’b000000;
end
else
begin
DR0_bypass_reg <= tdi; //Update the Bypass Register Just in case the incoming data is not sent to DR1
if ( v_sdr ) // VJI is in Shift DR state
if (select_DR1) //ir_in has been set to choose DR1
DR1 <= {tdi, DR1[6:1]}; // Shifting in (and out) the data
end
end
//Maintain the TDO Continuity
always @ (*)
begin
if (select_DR1)
tdo <= DR1[0];
else
tdo <= DR0_bypass_reg;
end
//The udr signal will assert when the data has been transmitted and it’s time to Update the DR
// so copy it to the Output LED register.
// Note that connecting the LED’s to the DR1 register will cause an unwanted behavior as data is shifted through it
always @(udr)
begin
LEDs <= DR1;
end
endmodule
This code was developed and derived with the help of some examples from the Altera Wiki
Clock Blinker
This is just a small block to generate a slow blinking indicator to tell us the design has downloaded to the FPGA and has started running.
module clk_blinker (
input clk,
output blink
);
reg [25:0] count;
always @(posedge clk)
count <= count + 1’b1;
assign blink = count[25];
endmodule
LED Connector
This block just rips the LED_Output bus down into the individual pin connections. I think there is an easier way to do this schematically, but this works for now.
module LED_Connector(
input [6:0]LEDs,
output wire LED_6,
output wire LED_5,
output wire LED_4,
output wire LED_3,
output wire LED_2,
output wire LED_1,
output wire LED_0
);
assign LED_6 = LEDs[6];
assign LED_5 = LEDs[5];
assign LED_4 = LEDs[4];
assign LED_3 = LEDs[3];
assign LED_2 = LEDs[2];
assign LED_1 = LEDs[1];
assign LED_0 = LEDs[0];
endmodule
TCL TCP/IP Server
The functions that we use to communicate to the Virtual JTAG instance inside our design are exposed inside the quartus_stp.exe
application. Presented below is a small Tcl script which runs in the quartus_stp.exe
that starts a TCP/IP server and pipes data to the DE0-Nano, thus giving access to the DE0-Nano design with virtually any programming language.
##############################################################################################
############################# Basic vJTAG Interface ##########################################
##############################################################################################
#This portion of the script is derived from some of the examples from Altera
global usbblaster_name
global test_device
# List all available programming hardwares, and select the USBBlaster.
# (Note: this example assumes only one USBBlaster connected.)
# Programming Hardwares:
foreach hardware_name [get_hardware_names] {
# puts $hardware_name
if { [string match "USB-Blaster*" $hardware_name] } {
set usbblaster_name $hardware_name
}
}
puts "\nSelect JTAG chain connected to $usbblaster_name.\n";
# List all devices on the chain, and select the first device on the chain.
#Devices on the JTAG chain:
foreach device_name [get_device_names -hardware_name $usbblaster_name] {
# puts $device_name
if { [string match "@1*" $device_name] } {
set test_device $device_name
}
}
puts "\nSelect device: $test_device.\n";
# Open device
proc openport {} {
global usbblaster_name
global test_device
open_device -hardware_name $usbblaster_name -device_name $test_device
}
# Close device. Just used if communication error occurs
proc closeport { } {
catch {device_unlock}
catch {close_device}
}
proc set_LEDs {send_data} {
openport
device_lock -timeout 10000
# Shift through DR. Note that -dr_value is unimportant since we’re not actually capturing the value inside the part, just seeing what shifts out
puts "Writing – $send_data"
device_virtual_ir_shift -instance_index 0 -ir_value 1 -no_captured_ir_value
#set tdi [device_virtual_dr_shift -dr_value $send_data -instance_index 0 -length 7] #Use this if you want to read back the tdi while you shift in the new value
device_virtual_dr_shift -dr_value $send_data -instance_index 0 -length 7 -no_captured_dr_value
# Set IR back to 0, which is bypass mode
device_virtual_ir_shift -instance_index 0 -ir_value 0 -no_captured_ir_value
closeport
#return $tdi
}
##############################################################################################
##############################################################################################
################################# TCP/IP Server ##############################################
##############################################################################################
#Code Dervied from Tcl Developer Exchange – http://www.tcl.tk/about/netserver.html
proc Start_Server {port} {
set s [socket -server ConnAccept $port]
puts "Started Socket Server on port – $port"
vwait forever
}
proc ConnAccept {sock addr port} {
global conn
# Record the client’s information
puts "Accept $sock from $addr port $port"
set conn(addr,$sock) [list $addr $port]
# Ensure that each "puts" by the server
# results in a network transmission
fconfigure $sock -buffering line
# Set up a callback for when the client sends data
fileevent $sock readable [list IncomingData $sock]
}
proc IncomingData {sock} {
global conn
# Check end of file or abnormal connection drop,
# then write the data to the vJTAG
if {[eof $sock] || [catch {gets $sock line}]} {
close $sock
puts "Close $conn(addr,$sock)"
unset conn(addr,$sock)
} else {
#Before the connection is closed we get an emtpy data transmission. Let’s check for it and trap it
set data_len [string length $line]
if {$data_len != "0"} then {
#Extract the First Bit
set line [string range $line 0 6]
#Send the vJTAG Commands to Update the LED
set_LEDs $line
}
}
}
#Start thet Server at Port 2540
Start_Server 2540
##############################################################################################
In order to run this server, I recommend you create a shortcut to the quartus_stp.exe
application, then modify the shortcut to execute this script like I’ve shown here:
When you run this shortcut the device should be detected automatically, and the server will start and begin listening for connections. It should look like this:
Python LED Counting Script
Here is the small script used to make a socket connection to the Tcl server, and send the binary string data to exercise the LEDs.
import socket host = 'localhost' port = 2540 size = 1024 def Open(host, port): s = socket.socket(socket.AF_INET, socket.SOCK_STREAM) s.connect(( host,port)) return s def Write_LED(conn,intValue): size = 7 bStr_LEDValue = bin(intValue).split('0b')[1].zfill(size) #Convert from int to binary string conn.send(bStr_LEDValue + '\n') #Newline is required to flush the buffer on the Tcl server conn = Open(host, port) for val in range(0, 2**7): Write_LED(conn, val) conn.close()
Summary
This tutorial demonstrates a proof of concept for creating a communication path between almost any programming language running on your PC and your digital design running on the DE0-Nano. In this example I’ve sacrificed detail for brevity, I think you’ll find that the Virtual JTAG User Manual explains very well the operation of that block. Feel free to leave a question in the comments section below if you are looking for more detail on any portion of this posting.
In the next blog post I’ll show how to simulate this design in ModelSim, I think this is an excellent way to understand how the digital design works.
In addition, just after I finished putting this post together I stumbled across a very rigorous, and more complex example of using this Virtual JTAG, and Tcl Server. In this tutorial the author shows how to connect the Virtual JTAG to an Avalon-MM master, find it here: Using the USB-Blaster as an SOPC/Qsys Avalon-MM master Tutorial.
i’m sorry but i’m not enough good for understand this tutoriel ^^ (maybe because i never use python)
Can you try to explain me your python code ? or did you know if someone do the same in c# (because my GUI is in C#)
i try to control some variable on the FPGA for help user in different case. the user willn’t need to know vhdl or C# code for change the configuration.
i’m sorry for my english ^^
Hello Chris, i couldnt see the link to download all the project files. Can you link me please 🙂
Hi Azri, my fault, a recent blog update broke the link. You should now find the link to the project files in the article above 🙂
Thank you Chris !. Keep up the good work 🙂
Btw, I have a problem. When I run the shortcut of quartus_stp, it shows that <>
it shows
“can’t read usbblaster_name: no such variable”
Hmm, interesting. If you open the TCL_Server_vJTAG_SimpleTest.tcl does it have the usbblaster_name variable defined? Such as is shown in the code above: http://imgur.com/a/BGi5O
Yes. It was defined at the top of script file. Hmm
http://imgur.com/f7e9ptf
Yes. It was defined at the top of the script file.
http://imgur.com/f7e9ptf
Interesting. I would wager that it’s unable to find your hardware. You could try uncommenting line 13 to show each iteration of the loop and see if anything is found. Most likely line 15 is never being hit, and that variable is not being set and thus throws this error.
Hello Chris, after uncommenting line 13, it does show the hardware name. http://imgur.com/UP4YfTT
Are you using a DE0-Nano? You can see that your hardware does not match the if statement on line 14 “USB-Blaster*” and this is why the variable is never set on line 15.
Oh yeah. Im using Deo Nano Soc.
It looks like the DE0 Nano SoC has a USB-Blaster 2 connection, so it should be possible to get it to work. Perhaps it’s just a matter of changing those programming DIP switches called out in the user manual.
Hello Chris,
I manage to solve the hardware name. But right now, i have another issue. When I compiled your python file. I have an error ” The specified virtual JTAG instance cannot be found”. Do you have any idea ? Thank you.
http://imgur.com/a/WaDr8
Hey Azri,
It looks like you have the TCL file is targeting the SoC and not the FPGA. Take a quick peek at what the JTAG configuration of your DE0-SoC is here: http://imgur.com/a/noGnd
I would uncomment line 25 and see if there are any other device’s available. You need to find a way to use the second target in the JTAG chain.
–Chris
Hi 🙂 .. Excelent tutorial.
I am lost in the way of sending data to python from the TLC code. I have modified the flags “-no_captured_dr_value” but I am not able to receive some data in Python .. I have read the comments you have made before but also do not understand why the communication is done bit by bit and not by blocks.
The “tdo” variable in the quartus project can not be of the vector type then??
Regards
Hi Daniel,
The way the Altera VJ-UART works is that you pass in 1 bit of data (tdi), then it passes out 1 bit of data (tdo). This is the reason it goes a single bit at a time.
In order to pass data back the other direction, you’ll need to make some big modifications to the TCL and Python server scripts to allow passing data back. If you want data communication that is more than just flipping bits in the FPGA as shown in my tutorial, you might take a look at the two projects I linked too in the edits at the top by Vern Muhr and Paul Green.
Hope that helps,
Chris
Hi Chris, thanks for your response.
Yes, I made a modification of TCL server to send data back, instead of “gets $sock line” I wrote something like “puts $sock myDataToPython” (of course read on Python that). I saw the other projects but I didn’t understand it jeje u.u (yours cost me to transform it first to VHDL before making modifications XD). I’ll keep trying, thanks again.
Regards
Okay, sounds good. Sorry I can’t be of more immediate help. Check back in and let me know if you’re successful in pulling data back the other direction. Best of luck!
–Chris
I recreated your example for the Cyclone II EP2C5 development board. The RTL is different, but the .tcl and .py files are essentially direct copies. It’s working fine. Thanks for your article (and follow-ups!), it was a great help to get me going.
The link to the project is when you click on my name. But here’s the full link also:
https://github.com/wallclimber21/ep2c5_vjtag
Awesome! I’m happy this post helped and thanks for sharing your code back with the community!
Hi Chris,
Thanks for the post. It is really good. I’ve replaced the python file with another language I am using. For this moment, I have a question: how can I receive data that is sent from de0-nano? For example, when PC send 0101 to de0-nano, I hope de0-nano can reply 1010 to PC. Which file should I modify? Do I need to change the tcl file?
Thanks
Tianbo Ji
Hi Tianbo Ji,
The way the vJTAG works is that for every bit you shift “in” you also shift a bit back “out”. You will just need to modify the portion of the vJTAG_Interface.v where the TDO line is being written to. (Find this comment in the code: //Maintain the TDO Continuity)
Additionally, you will need to modify the tcl file because we are currently not capturing that shifted data, I’m using the “-no_captured_dr_value” flag. You’ll need to change this and capture the data coming back and then modify the code to allow you to send that back over the TCP/IP connection.
You might also look to the project I referenced at the top of this post. It does look like the Open_Sld project has the ability to read back the data: https://github.com/GeezerGeek/open_sld
Hope that helps point you in the right direction.
Best regards,
Chris
Hi Chris,
Thanks for your advice. Now I’ve modified the tcl file to let it put the shifted data back to my Haskell TCP client successfully. But actually I am not a Verilog user so I may have to replace all the .v file by .vhd file. As you said, you got the sld_virtual_jtag file from the Altera Megafunction Wizard. I want to know whether it has a vhdl version? If not, I will try to rewrite it. Again, thanks for your help.
Regards,
Tianbo Ji
Cool project!
You provided a really good example, complete from vJTAG interaction inside FPGA to TCP server on PC side, and also Python client for it.
It helped me to finally understand how this vJTAG is supposed to work.
I suspect it would not be difficult to modify this into a debug server for homebrew CPU.
On a side note, you could implement a USB host with virtual RS232 (Or virtual flash drive? Or maybe HID keyboard?) interface for PC communication. It would be much more versatile, in exchange for some extra logic use, extra USB cable and 2200 Ohm resistor.
Thanks for the kind words Evgeniy.
I was hoping to avoid having to add a second USB cable, so this was my main motivation for working with the vjTAG. That being said, there is definitely room for extending this project into a more useful debug system.
Hey you really did a good job!
But can these project be better?
In this project we learn how to command de0-nano to do something.
We learn how to “talk to” it!
But can we learn more about how to “listen from” it~?
I mean, can we get some data from de0-nano in similar way~?
After all, communication are based on “talk” and “listen”, haha
If you do have time, can you give us more information about this~?
Just some simple demo like show the LED pattern on the command window helps a lot!
Let I appreciate this useful post again! It is very helpful!
Very Good Post!
The example is very useful!
Here I have some questions :
(1). What the input ‘tdo’ and ‘ir_out’ of the vJTAG megafunction do?
In vJTAG_interface.v, tdo continuosly catch the data from bypass shift register or DR0 to maintain
its continuity, and then send it to vJTAG’s tdo input.
what’s does the tdo do in this project~?
Besides, is ir_out a necessary part in this project?
(2).Can I utilize tdo to send some data from fpga to the interface and to my PC?
If yes, what should I do in the tcl script to get data from tdo?
(3). What difference lies between device_virtual_ir_shift and device_ir_shift
and similarly between device_virtual_dr_shift and device_dr_shift?
I see theses function in the document but cannot get them
Thanks for your post again and hope you can give me some feedback about my questions, Thanks!
Hi Wire, all good questions. I found this guide useful when learning how JTAG works
http://www.fpga4fun.com/JTAG.html
It will cover most of what you are asking here. The Altera virtual JTAG mega function guide will answer the other points.
The examples in this post are kept simple to demonstrate the functionality, so try them out and you will find that, yes you can send information from your Altera JTAG adapter to your PC.
Good luck.
Hey there, Really nice guide. It was really helpful.
I have combined codes from Vern Muhr, Paul Green and your post and made a Wishbone compliant JTAG UART module to let my FPGA communicate with my computer, without any extra cables and dependencies like Quartus. And it works just like you’re using a regular UART on a microcontroller.
Instead of Python, I ported it to C#, because it was easier for me.
Hi Ali,
Well done! It would be great if you could share your project with us. Since it’s Wishbone complaint, maybe you have uploaded it to OpenCores already?
C# is great! I’ve been working with .NET a lot lately, so no problem for me. Maybe we can wrap the functionality as an API and expose it for the python (other lang) users.
Looking forward to seeing and using your accomplishment!
It has two little bugs in it on the FPGA to Computer direction.
One from FPGA to the JTAG of DE0-nano (in VHDL) and another in the reception of the data to the client app (C# program that I wrote).
I’m sure that the VHDL bug won’t be difficult to fix. I haven’t given it much time.
Btw, I’m also done with writing the client app in Python. But it has exactly the same bug as in my C# client app. I’m making the same mistake somewhere in both languages 😉 Strange.
It works perfect when small packet of data is sent. But when a large packet is sent, it misbehaves.
I’ll upload the code next week after getting free from work. And see if anyone can help me fix these two bugs.
Hi
Very nice job all (Vern Muhr, Paul Green, Chris Zeh and Ali Yousuf)
I also try to communicate with my USB-JTAG device from python script without quartus_stp or quartus_pgm to my custom Virtual JTAG machine.
But it seems that your example does not support multiple devices in JTAG chain, confirm ?
Regards.
Hi illico,
Thanks for the compliments. No response yet from Vern, Paul, or Ali, but my guess is their interface doesn’t yet support multiple devices in the chain. If you get it working, please drop by and let us know.
Best regards,
Chris
Sorry its taken so long so reply, work gets in the way! The logic in the core virtual JTAG interface does allow a bypass, so ensure you have issued the bypass command if you are addressing more than one device in the chain. Bypass command is the usual all-1s, prefixed by the device node id.
The code in/out definitely are not chain friendly and the capture DR followed by DR shift does not take into consideration anything coming down the TDI line.
One alternative that I would recommend is to use a separate SLD node for each piece of functionality. Altera allows you to keep your logic separate by giving each SLD an address. The example code just uses address 1, but equally you could have independent addresses for nodes in your ‘chain’. This uses more of the FPGA core, but simplifies your interface.
Hope that helps.
[…] Fortunately, Altera’s Virtual JTAG functionality allows easy access to logic inside of your design. Chris Zeh wrote an excellent article on this Virtual JTAG functionality and how to easily send data in and out of the chip. You can read his blog entry here. […]
Chris, I was super inspired by your article and I took your STP example and built a “virtual comm port” using Quartus STP and TCL. The proof of concept is a verilog state machine that sends the A-Z through telnet to the PC, then echoes every character typed. Pretty cool with no additional hardware! I’d like to make it available as a template to anyone that wants it because it’s probably the most wanted feature lacking on the DE0-nano. Happy to provide the files to you for posting on your blog?
Cheers, Paul
Hey Paul,
This sounds like an awesome project! If you want to push the files up to GitHub, and send me a link, or leave it here in the comments, I would be happy to give the project a try, and publish a write-up on how to use it.
If you don’t want to bother with GitHub, feel free to zip up the files and send them my way and I’ll just include them as a download w/ the writeup.
Email:
Best regards,
Chris
Sorry i didn t explained it much 🙂 Yes everything works with quartus tool, the problem is communicating with the device using the ‘Vern’s solution’ 🙂
libftdi on linux and libftd2xx didn t see my de0 nano and didn t understand why (even the statictest from the lib didn t see it)
Thx for your reply. Currently my fpga is commanded via an amd64 pc, but the purpose is to bypass that and command it directly from raspberrypi :p
Hi Khertan,
Okay, I think I might be able to help a little bit.
Take a look at this link:
http://idle-logic.com/2010/12/13/libftdi-v0-18-with-ubuntu-lucid-lynx/
I also had problems getting the libftdi to see a FTDI chip using Linux. In my post I was using a FTDI FT232RL, I’m pretty sure the DE0-Nano is using a different FTDI chip, I think the FTDI 245BM, I don’t recall exactly, so you might have to modify the VID/PID I used (it might be the same). Hopefully that will get you going down the right path.
Really interesting.
Thanks, unfortunatly i ven t been able to make it working on linux (Debian Wheezy). My de0-nano isn t found, nor listed.
Any advices ?
Thx
At which point is the DE0-Nano not found, can the Quartus programmer find it at all? Is it just the quartus_stp.exe that can’t find the Virtual JTAG node, or are you using Vern’s solution, and it can’t be found that way?
Hi Paul,
The upper bit is the address of the SLD node. In this case it is 1. The lower four bits are the command. As I understand it, the minimum command width is 4 bits, even though only bit 0 is actually used.
Hi Paul,
It is working in the latest version on github (https://github.com/GeezerGeek/open_sld).
The test program now prints the data read back as the program runs. The data is the previous contents of the virtual_data register. For example, when 5 is being written, 4 is read back.
Hi Dave:
I can run quartus_stp from command line of windows, but we i ran quartus_pgm from command line, it seems meeting problem. How did you set your environment system variables?
BTW, what the function of sub_process?
Hi All,
I’m interested with downloading sof using Python. I read Vern’s code, it seems that quartus_pgm can be call directly inside Python code?
But, i add simple line “command_line = ‘quartus_pgm -c USB-Blaster -m JTAG -o p;my.sof'” in my Python code, and it didn’t work, why?
Hi Dears:
Can you access open_sld by using c/c++? ^0^
It’s really hard for me to understand python language.
In my machine this works. I had to modify the code so that I worked. First I had to obviously add the path of quartus_pgm in the environment system variables. Then I had to modify the sub_process function call in sld_interface.py like this:
#retcode = subprocess.call(command_line)
retcode = subprocess.call(command_line, shell=True)
Now I can see the LEDs changing in accordance to the control.
Regards,
Dave
Nice, thanks for reporting your success! I haven’t had time to try it yet, but by reading Vern’s code alongside the Virtual JTAG Megafunction documentation, I’m beginning to understand how the communication path works from JTAG/TAP -> SLD -> VJI/Design.
I still need to spend some time to understand how the FT245/CPLD/FPGA are connected and what the CPLD is doing to the data stream.
Hi Chris,
I just put it up here https://github.com/GeezerGeek/open_sld
Best regards, Vern
Hi Vern,
This is awesome! I’ve taken a quick look through the code and it looks great. Well documented, and the debug features look really helpful. I’m really happy with the potential to get rid of the TCL and TCP/IP pipe.
I’ve done some work in the past to program an Altera FPGA bitbanging an RBF file through a FT232RL. (http://idle-logic.com/2011/03/05/programming-an-altera-cyclone-ii-fpga-with-a-ft232rl-python-code/)
I bet with a little work it could be possible to bypass having to use the quartus_pgm to program the device and do it directly via the FTDI.
I have to spend some time to better understand the CPLD logic and how the TAP and Virtual JTAG work to fully understand your code.
I’ll report back when I’m successful using your open_sld.
Thanks again,
Chris
Vern,
I tried playing around with your code and got it working wonderfully to send a byte at a time to the DE0-nano. (I changed that silly Quartus design that blinks lights randomly instead of some clear indication of proper functionality).
I was wondering what Altera document you used to develop the SLD controller. I am going to try to send data the other direction (from the FPGA to my python code), and I was wondering if you have any suggestions to point me in the right direction.
Thanks,
Paul
Here are a couple of links I’ve been looking at in addition to the ones mentioned in Vern’s github project readme:
http://www.altera.com/literature/ug/ug_virtualjtag.pdf
http://sourceforge.net/apps/mediawiki/urjtag/index.php?title=Cable_Altera_USB-Blaster
“silly Quartus design that blinks lights randomly instead of some clear indication of proper functionality”
Binary counting is random and isn’t a clear indication of proper functionality…?
Chris,
Didn’t mean to be rude–I just found it hard to simultaneously check 1 heartbeat LED + 7 LEDs counting binary at that speed, and I changed it to a (0x01,0x02,0x04,0x08,…) shift sequence that bounces back and forth on the DE0-nano’s row of LEDs.
I spent a couple hours trying to get reading to work, but have not been successful yet. It looks like Vern’s code has M0D0R and M0D1R bit sequences but doesn’t really demonstrate or document how to read data shifted from the jtag interface block into the vJTAG megafunction. I suppose “R” stands for read, but when I use the read() function (self.interface.read()) I don’t get [the right] data out. I think I’m not initializing something correctly before trying to read the ftdi buffer using self.interface.read(nBytes). If anyone has gotten it to work I would love to know how.
-Paul
Oh, and one other thing: does anyone know where the ‘10001’ and ‘10000’ instruction sequences that straddle VDR_Write commands are documented? Is that something Vern reverse engineered? They’re pretty cryptic compared to the well-documented state-transitions from page 36 of the Altera vJTAG manual.
-Paul
Hey Paul,
Okay, understood.
I still haven’t had time to play around with Vern’s code, but you should check out his latest commit on Github, it looks like he’s working on adding Read capability.
As for the seemingly arbitrary VIR writes, if I’m not mistaken these are the commands that switch my design between select_DR0 and select_DR1. However, I think they only need to be 0 and 1. I’m not certain the purpose of that higher order bit.
Hi,
I just finished a proof of concept for running your example from pure python code without TCL & quartus_stp in the middle. I used the ftd2xx.dll, and a python ctypes interface written by Jonathan Roadley-Battin. It communicates directly with the InitialTest sld node using JTAG directly.
Python also loads the .sof file before running the test.
Let me know if you are interested in the source files.
Best regards, Vern
Hi Vern,
I would be very interested to see how you were able to interface with the JTAG using ftd2xx.dll. I think myself and a lot of people would like to bypass having to use the quartus_stp to communicate.
Please send it my way at: Chris@idle-logic.com, or leave a link to dropbox/github/etc in the comments.
I’m familiar with the ftd2xx and ctypes. Did you reverse engineer the commands quartus_stp sends, and recreate them talking directly to the FTDI IC?
Thanks for sharing your discovery, and no doubt hard work!
Best regards,
Chris
[…] I still have some work to do to improve the ModelSim/Quartus workflow, and create a more robust communication framework between the PC and DE0-Nano via the USB […]
Cool 😀 and tested 🙂
Thanks for this summary 😀
No problem 🙂
while interfacing my de0 nano board to my pc it is interrupting it by containing jtag_clien.dll is missing from your computer.how can i resolve this issue please notify me …….
Thank you so much for this!!
No problem, glad it was helpful!
Hi Chris,
Thanks for you kindly help1
You’re welcome!
Hi Chris,
My question is that you must use quartus_stp to start your server, just as your article figure TCL Server shows.
So if i understand correctly, we have to do like that? Even we setup the communication by TCP/IP, we at least using TCL and quaruts_stp to start the server of the TCP/IP socket. Am i right?
Ahhh okay. I understand now. Correct, as far as I know, the only way to use the TCL commands that talk to the vJTAG are to run the TCL script with the quartus_stp.exe.
I don’t recall 100%… it might be possible to use the vJTAG commands in other Quartus exe’s, but you can’t use those functions for example in ActiveTCL.
Hi Chris,
Another question, we know that we discuss client-server here because we want to use other language (for exampe C++) to design user graphic interface to access vJTAG hardware. However, just like your above article, your client program can designed using other language, you must still use TCL and quartus_stp to implement your server program. Is it possible that someone who is not family with script and vJTAG can design them (client&server)without script?
Hi Jerry,
I’m not sure if I understand your question.
The vJTAG API is not open, so we can’t directly talk to the vJTAG without using the quartus_stp software from Altera, so we will always need the communication to go through quartus_stp, either by TCP/IP, or some other piping technique.
Sorry, i found why the first question happen. It becasue i only used one “gets $s line”.
It seems i should use three times above code when i send three lines, as below:
puts $s “Hello!”
#gets $s line
#puts $line
puts $s “Thanks!”
#gets $s line
#puts $line
puts $s “You!”
gets $s line
puts $line
gets $s line
puts $line
Hi Chris:
I resolved my issue now after modify according your codes. Thanks for you help.
Another two questions need you help:
1. I send three lines in client program, and i can receive them in my server program, but i just only receive the first line in client after server send them back to client. I send them back as your above code by using “puts $sock $line” in server.
2. What’s the difference between “#fileevent $sock readable [list Echo $sock]” and “fileevent $sock writable [list Echo_wr $sock]”? I can’t find any difference between them after running in my codes.
Hi Jerry,
I’m not sure how to answer your question #2. Interesting that interchanging writable and readable has no effect.
I guess all the more reason to pipe out the vJTAG commands away from TCL programming and use a different programming language 😉
Hi Chris,
Thanks for you reply, I’ll try your code next week!
You’re welcome. Let me know if that gets you going. Have a nice weekend!
It seems the state “puts $sock $line” caused this error.
Hi Jerry,
There is a problem with the http://www.tcl.tk example code (which I fixed in my code).
The problem is that once the Client disconnects it appears to transmit basically an empty string which causes the puts ‘$sock $line’ to fail.
The quick fix is to check to make sure the incoming data is not empty. So, in the Server code, change the Echo proc to the following:
proc Echo {sock} {
global echo
# Check end of file or abnormal connection drop,
# then echo data back to the client.
if {[eof $sock] || [catch {gets $sock line}]} {
close $sock
puts "Close $echo(addr,$sock)"
unset echo(addr,$sock)
} else {
#Check for and empty strings first:
set data_len [string length $line]
if {$data_len != "0"} then {
puts $sock $line
}
}
}
Hi Chris,
Have run the example from http://www.tcl.tk/about/netserver.html?
I went to that website and try to run that example, the client can echo the server, but i receive an error. I copy the tcl into two tcl script files. One for server, another for client. I didn’t change anything. Below is the client script file:
proc Echo_Client {host port} {
set s [socket $host $port]
fconfigure $s -buffering line
return $s
}
set s [Echo_Client localhost. 2540]
##set s [socket localhost 2540]
fconfigure $s -buffering line
puts $s “Hello!”
gets $s line
I excute the server script firstly, and the command line show “Started Socket Server on prot – 2540″.
Then i excute above client script, it can invoke the EchoAccept procedure, and in the command line i will receive below informations:”
Accept sock1440 from 12.0.0.1 port 2477
error writing “sock1440”: connection reset by peer while excuting
“native_puts sock1440 {}” invoked from within “eval native_puts $args” invoked from within “puts $sock $line” invoked from within “Echo sock1440”
“
You mean other language (for exampe C/C++) can access vJTAG by using this clint/server structre indirectly?
Yup, exactly.
I don’t know why did you want to design the TCP/IP clint-server? We can access vJTAG directly.
As far as I know, the API for communicating with the Virtual JTAG interace is not open (sld_hapi.dll), and can only be accessed by running TCL scripts within quartus scripts.
Is there some other way to communicate to a vJTAG instance outside of TCL & Quartus tools?
Chris, i m using version 12. the quartus_stp.exe was written and size turned zero. it is quite annoying and i dont know how to avoid this from happening again.
Brian
That’s really strange, I have not had that happen. Might be time to upgrade to Quartus v13.
Hi Chris,
I am modifying your verilog code and hope to transfer a packet of around 12 bytes each time. It seems to me that it takes a few seconds to send all the 12 bytes. Just wonder where is the bottleneck of the data transfer speed. Possible to make it a lot more faster, say dozens of milliseconds to transfer 12 bytes?
Hope you can advise me on this.
Regards,
Brian
Hi Brian,
One of the bottlenecks mentioned above in the comments is the fact I’m opening and closing a connection every time I wish to send a byte. Using something like pockpock mentioned above should speed things up.
I haven’t spent much time profiling the code so I’m not sure where it’s slowest. You probably should be able to modify the code to instead of shifting one byte at a time, but shifting the full 12 bytes in one shift command (maybe you already did this?)
I’m hoping Altera will just open up the Virtual JTAG communication API some day so we no longer having to do this TCP/IP pipe which no doubt is slowing things down.
Hi Chris,
Thanks for your reply. I tried shifting all 12 bytes in one shift and it works. Speed enhanced a lot.
Regards,
Brian
Excellent!
Hi Chris, it found it twice that quartus_stp,exe corrupted somehow and need to be reinstalled. did you encounter the same before? and do you know where can i download it again? without installing quartus?
Brian
Oh wow. Yeah, I’ve never had this happen. Which version of Quartus are you using?
[…] put together a little list of my more popular posts here on Idle-Logic.com: Talking to the DE0-Nano using the Virtual JTAG interface.Shows a technique to setup a communication path between the PC and DE0-Nano using the existing USB […]
Oh dear :-)) And here is me checking my hotmail account again and again and (secretly) hoping to find your reply there. Only after having given up all hope did it occur to me to look… where I had posted my question in the first place!! Thank you so much again.
Now I have downloaded the vJTAG_DE0-Nano_Example.zip file.
I can start the InitialTest project in Quartus II (my version is 10.1) and after compiling and starting it, I see how the DE0-Nano reacts (LED7 blinks and all other LEDs are off).
Then I copied the TCL_Server_vJTAG_SimpleTest.tcl in Quartus\bin64, and tried 100 times to run it with quartus_stp – but it wouldn’t work (SignalTap II error). And then I realized I had left out the -t argument from your instructions!!! Now it works!!!!!!!!!!!
Thank you very much again!!
Marcos
Hello Chris,
Thank you very much for your posts. Admirable and inspiring is the least one can say!
I have tried to follow the steps you describe, but always come to a halt at the TCL-Server part. I don’t understand how the quartus_stp.exe is supposed to set-up the connection and neither can I find the TCL_Server_vJTAG_SimpleTest.tcl file you mention in the tutorial.
You see, I am not quite initiated in the FPGA world. I would be very grateful if you could give me a hint.
Thank you very much anyway!
Marcos Gonzalez
Hi Marcos,
You’re quite welcome! I’m glad you were able to find this post, and hopefully I can help get you up and running.
The quartus_stp.exe application has the “secret” API commands that allow communication via the Virtual JTAG Hardware that we put into the FPGA. Because of this, we have to run our TCL_Server_vJTAG_SimpleTest.tcl file inside the quartus_stp.exe command line application. When this script is running it basically opens a communication path from TCP/IP through to the device. We can then talk to the TCP/IP interface using almost any programming language.
In order to find that .tcl file, you need to download and open the Download vJTAG_DE0-Nano_Example.zip file above. Once you’ve downloaded it, you will find an archived Quartus project within. If you run that file it will extract the project to a directory you specify. Quartus itself will not show you the TCL_Server_vJTAG_SimpleTest.tcl, but if you open your File Explorer to the directory in which the project was extracted and you should find it there.
Or you have the option of Copy/Pasting this file, which is shown in it’s entirety, above in the tutorial.
Hopefully that is helpful, let me know if you are still stuck and I can try to help more.
Very detailed. All I have to do is try it! Thanks always.
No problem, good luck!
Hi Chris. Great example. However, I am trying to establish data transfer from FPGA to PC. I will control the FPGA run with the external switch. Upon completion of the internal run, collect the results from FPGA. It is as if I am using the FPGA as a simulator, and wanna get the results into a file. You have any idea how I can do it using the vJtag (or if I can even do it)? Thanks…
Hey! Thx a lot for the tuto…
Im trying to send data form fpga to pc following by your tuto but im rlly lose, did you make/have any example???
Thx!
Hi, you’re welcome! Well… the tutorial basically is the example. In the article you can find a zip file download that contains all the files. Let me know where you are confused, or stuck and hopefully I can help get you going.
Hi,
I thank you for this tutorial
You’re welcome! Thanks for stopping by and leaving a comment.
Hi Chris,
I hope you are doing well.
I want to read switch and button status of the board via the JTAG, have you ever done before? can you send me an example?
regards,
Abderrahim
Hey Abderrahim,
Unfortunately, I haven’t yet put together this kind of functionality. I have a few other projects that are taking up most of my time right now, but I’ll try to put together an example some time soon.
If you can’t wait for me, try asking on the Altera forum,.
Thanks,
Chris
Hey Chris,
anything new in communicating from the de0 to the pc via vJTAG?
best regards,
Quasar
Hi Quasar,
Unfortunately, I’ve been tied up on some other projects for the last few months and haven’t had time to build on this topic recently. Be sure to subscribe to the RSS feed if you haven’t already to get the new posts as soon as they come across.
I have a few VB.NET related programming posts queued up, then I’ll be returning to the DE0-Nano and JTAG communication.
hi folks, if you’re using python 3.2, change the following lines:
——————————–
def Write_LED(conn,intValue):
size = 7
bStr_LEDValue = bin(intValue).split(‘0b’)[1].zfill(size) #Convert from int to binary string
conn.send(bStr_LEDValue.encode(‘utf-8′) + b’\n’) #Newline is required to flush the buffer on the Tcl server
—————————-
otherwise .py file might throw exception
Great tip, thanks Michael!
Thanks Michael, (August 8, 2012 at 9:26 am – comment)
I´m using python 3.5 x64 and it´s work like a charm before made the changes that you suggest!
Regards
Hi Chris,
Thank you for your answer.
I work with Quartus II 11.1 (32-Bit).
I’ve the function Write_LEAD in your script deactivated.
——–
def Write_LED(conn,intValue):
size = 7
bStr_LEDValue = bin(intValue).split(‘0b’)[1].zfill(size) #Convert from int to binary string
conn.send(bStr_LEDValue + ‘\n’) #Newline is required to flush the buffer on the Tcl server
——–
instead of this, I have sent a strong message conn.send(‘1110111\n’), the Board has responded to my message.
Now I can develop a GUI, many thanks again.
Best regards
Abderrahim
Glad you were able to get it going. Have fun!
Hello,
reading your tutorial was very intersting for me.
I followed all steps till server (quartus_stp) start and LED8 was blinking.
Then using Python LED Counting Script didn’t lead to a succssful server connection.
How can i create a connection to server(quartus-stp), do i need a jtag_client.dll or does it work with
vJTAG_DE0-Nano_Example.zip?
I’d like to exercise the LED via GUI.
Thank you for your input.
Abderrahim
Hi Abderrahim,
Hopefully I can try and help you out:
Everything you need should be in the zip file, and no need for additional .dll’s.
Which version of Quartus are you running?
Any chance Firewall software is blocking the TCP/IP ports we are using to make this Python to quartus_stp connection?
Is the quartus_stp TCL script running and opening a server port correctly?
As I suspected, the slow part is opening/closing the port. Actually sending data is quite fast. I modified the TCL code to only open the port and lock the device once per connection, and hacked the Python code to repeat each message 256 times. The counter now takes about 10 seconds to complete, which means 128*256 bytes / 10 seconds is about 3kbps. Now that’s from inside VirtualBox using a USB1.1 forwarding layer and without really thinking any about what’s going on. But as is, that’s plenty fast for my use case. Thanks, you made this really easy to get going!
And of course I meant 3 kBps (about 26 kbps).
Hi Kenneth,
I’m glad you were able to get it working. Thanks for reporting back your improvements and speed metrics! For sure this communication path isn’t a speed demon, but will hopefully be good enough for a lot of designs.
Hi Kenneth
Can you please supply me with the TCL and any other code you changed in order to fasten the writing to the DE NANO.
Thanks
Ofer
This would be very interesting for me too, because at the moment i receive data with a rate 2Hz, on an other computer with 13Hz and that is too slow for my application.
He already said what he did: he moved the lock of the JTAG device so it would only be called once per connection.
This works for me:
proc ConnAccept {sock addr port} {
…
puts “connection: from $addr port $port”
openport
device_lock -timeout 10000
….
}
proc IncomingData {sock} {
…
close $sock
puts “disconnected $conn(addr,$sock)”
unset conn(addr,$sock)
closeport
…
}
And ofcource remove/comment these lines:
proc set_LEDs {send_data} {
…
#openport
#device_lock -timeout 10000
…
#closeport
…
}
PS: thanks for this guide, it is far more clear than alteras documentation.
Can you please send me the code for the mods you did up to this point? I just need the new TCL script and the corresponding python script. I did this several months ago and it perfecly worked but I lost the files in a computer that died. I would appreciate if that is possible. If you can you email it to me: wp4hnf@hotmail.com. Thanks, San
Thanks! I made the changes you mentioned and now it works.
About the problem I told. I had the original code:
for val in range(0, 2**7):
Write_LED(conn, val)
and the connection was closed somehow. The last written word was 0001111 (I could see the leds) and then the tcl-window tells “The connection reset by peer”.
But now, the problem is passed, thank to you advices. Now, I try to find out what is the data rate of the connection and if it’s enough to my app.
-Jouni
Glad it’s working for you. Hopefully it will be fast enough for your needs. My initial experience suggested that the data transfer rate was pretty slow, although I didn’t try to find the bottle neck. It might just be that printing out to the console was slowing it down.
Good luck!
Hi Jouni, thanks for the kind words. Let’s see if I can help…
When you say the error happens “before writing 0010000” does that mean writing the LEDs 000000 to 0011111 the readback works, but once you hit the next setting it fails?
My gut feeling is that you need to send a newline (\n) character from the TCL side to flush the buffer out, but since you are only requesting 1 byte in Python, maybe this isn’t the problem…
Hi Chris and thanks for this good post!
This is my first touch to tcl and I wonder how can I read data from the FPGA. Have you done the reading process from FPGA? I tried to make it (some minor changes in tcl and python scripts) but “the connection was reset by peer” before writing 0010000. The connection was stopped during the transmission.
Regards,
Jouni
ps. Minor changes:
#—————Tcl:————————–
proc set_LEDs{send_data}{
…
set tdi [device_virtual_dr_shift …
#device_virtual dr_shift …
puts “Read – $tdi” #Debugging
…
return $tdi
}
proc IncomingData{sock}{
…
#Extract the First Bit
set line [string range $line 0 6]
set recdata[string range $line 0 6] #Variable for reception.
#Send the vJTAG Commands to Update the LED
set recdata [set_LEDs $line]
puts $sock $recdata
…
}
#—————Python:—————-
def Write_LED(conn,intValue):
…
conn.send(bStr_LEDValue + ‘\n’)
data = conn.recv(1) #Client receives a byte.
return data
for val in range(0, 2**7):
d = Write_LED(conn, val)
print d
Hey Jouni, I had some time to play around with the code…
If you delete this line:
set recdata[string range $line 0 6] #Variable for reception.
and increase your recv buffer:
data = conn.recv(9)
…your code changes work.
(Each binary bit is sent as a character string, so 7 bytes plus a CR and LF character)
No need to add an extra newline like I mentioned in my comment above, “puts” does this for you.
(Watch out, I’m just learning that TCL doesn’t know what to do with comments at the end of a command. So in my original code where I have this code commented out:
#set tdi [device_virtual_dr_shift -dr_value $send_data -instance_index 0 -length 7] #Use this if you want to read back the tdi while you shift in the new value
If you uncomment this line, be sure to delete the trailing comment or it will fail.)
Let me know if you still have trouble.
[…] Here I’m going to demonstrate how to use ModelSim to test out the Virtual JTAG design that I showed in my previous post. […]
Hi Chris,
Now works fine!
Thanks
Leonardo
Hi Leonardo,
Thanks for taking a look.
1) Looks like an extra file snuck into my deployment. I’ve uploaded a corrected QAR file. Either try this new file, or you can just remove that vJTAG_inst.v from your project, it’s unused. (It’s was automatically generated by the MegaFunction wizard to demonstrate what code you would need to use in a Verilog file to instantiate the vJTAG block. I use a schematic so we don’t need it. Sorry about that.
Let me know if you have any problems now.
2) From what I’ve been reading it may be possible, but difficult. We have to find some way of calling those vJTAG functions via the DLL that quartus_stp.exe uses. Unfortunately, Altera doesn’t have a nice exposed API for us to play with, so we would have to do some heavy lifting to figure it out. A big project for another day.
3) This solution will let you send data much faster than the vJTAG. As with most connections to the FPGA you’ll need to be careful to match the I/O Voltages, but you shouldn’t have too much trouble connecting this module. The DE0-Nano user manual lists the I/O Standard for most of the exposed pins, I believe they are all 3.3V. So as long as you don’t connect any 5V level signals you’ll be fine.
4) One project I have in the pipeline is to start working with an embedded softcore NIOS CPU inside the DE0-Nano, this gets rid of the need to use an external MCU. However, it would be nice to learn about the different I/O specifications (LVTTL, etc) at some point down the road.
Thanks for the feedback!
-Chris
Very good post!
I have some questions:
1)When i compile with Quartus 11.1 SP2 I get:
Error (10170): Verilog HDL syntax error at vJTAG_inst.v(1) near text “(“; expecting “;”
Error (10839): Verilog HDL error at vJTAG_inst.v(1): declaring global objects is a SystemVerilog feature
How can i fix this?
2)It is possible in some way communicate without quartus_stp.exe but directly with a C# program using VJTag?
3)I have an USB to Serial TTL Module (http://www.aliexpress.com/product-gs/492071325-CP2102-Serial-Converter-USB-2-0-To-TTL-UART-6PIN-Module-OT814-wholesalers.html), is very cheap but is more dangerous use this with two I/O pin instead of VJTAG?
4)What about making post on DE0-Nano pin I/O and how interacting FPGA with an MCU (for example Arduino)? There is not much documentation about LVTTL, etc..
Very good work
Keep posting
Ciao
Leonardo