DE0-Nano | Idle-Logic

Archive for the ‘ DE0-Nano ’ Category

Talking to the DE0-Nano using the Virtual JTAG interface.

April 15th, 2012
Posted in Altera . DE0-Nano . Python . Tcl . vJTAG

How to communicate between a PC and a design running on the DE0-Nano using the Virtual JTAG Megafunction, a Tcl TCP/IP Server running in quartus_stp with virtually any programming language. The first thing I wondered when I got my hands on the DE0-Nano was how best to communicate with a design inside the FPGA. Initially, [ READ MORE ]

Using ModelSim with Quartus II and the DE0-Nano

December 4th, 2011
Posted in Altera . DE0-Nano . fpga . ModelSim

This is a tutorial to walk you through how to use Quartus II and ModelSim software together to create and analyze a simple design (an inverter), then we’ll compare the RTL and Gate-Level simulations with the results on a DE0-Nano. This tutorial assumes you have some basic experience working with Quartus II. Going through the [ READ MORE ]

Welcome the DE0-Nano

October 13th, 2011
Posted in Altera . DE0-Nano . fpga

My posting this summer, due to outside obligations, has been ridiculously sparse. (Literally ‘outside obligations’: I’ve been landscaping my yard all summer). I’m starting to have a little more idle time now that the summer is winding down, and now my motivation has been completely revitalized by this little guy: The DE0-Nano development board from [ READ MORE ]

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Here you will find details on the latest projects, musings and other content from the brain of Chris Zeh.

Chris' favorite topics range from Electrical Engineering and Physical Computing, to Programming and Web Development.

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Talking to the DE0-Nano using the Virtual JTAG interface.

Using ModelSim with Quartus II and the DE0-Nano

Welcome the DE0-Nano

What is this site about?

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