That is one option, however at the time I wanted to continue using those CBUS pins for their other features (48MHz CLK, RD & WR strobe).

With a few MUX’s we might be able to use only 1 CBUS pin to switch between config and general mode.

While I was in the middle of sourcing the MUX’s I needed I stumbled across the DE0-Nano. Since it was so much cheaper than anything I could put together I decided to abandon my little bare-bones FPGA project.

Let me know if you get it working, I’m curious if the CBUS is any slower programming the FPGA than the BitBanging on the main port.

Best regards,
Chris

‘(Teaser: I’m currently working on a MUX system that will allow us to “reconnect” those FT232RL pins to I/O pins of the Cyclone II, instead of always being connected to the FPGA’s config pins. With a little work it should give us the ability to program and communicate with the FPGA for less than $15! )’

The FT232RL has an extra 5bits (CBUS) you could use 3 of these bits to configure the FPGA leaving the main 8BIT bus free for communication. I am will be trying this approach my self very soon

Now works fine!

Thanks
Leonardo

Thanks for taking a look.

1) Looks like an extra file snuck into my deployment. I’ve uploaded a corrected QAR file. Either try this new file, or you can just remove that vJTAG_inst.v from your project, it’s unused. (It’s was automatically generated by the MegaFunction wizard to demonstrate what code you would need to use in a Verilog file to instantiate the vJTAG block. I use a schematic so we don’t need it. Sorry about that.

Let me know if you have any problems now.

2) From what I’ve been reading it may be possible, but difficult. We have to find some way of calling those vJTAG functions via the DLL that quartus_stp.exe uses. Unfortunately, Altera doesn’t have a nice exposed API for us to play with, so we would have to do some heavy lifting to figure it out. A big project for another day.

3) This solution will let you send data much faster than the vJTAG. As with most connections to the FPGA you’ll need to be careful to match the I/O Voltages, but you shouldn’t have too much trouble connecting this module. The DE0-Nano user manual lists the I/O Standard for most of the exposed pins, I believe they are all 3.3V. So as long as you don’t connect any 5V level signals you’ll be fine.

4) One project I have in the pipeline is to start working with an embedded softcore NIOS CPU inside the DE0-Nano, this gets rid of the need to use an external MCU. However, it would be nice to learn about the different I/O specifications (LVTTL, etc) at some point down the road.

Thanks for the feedback!
-Chris

I have some questions:

1)When i compile with Quartus 11.1 SP2 I get:

Error (10170): Verilog HDL syntax error at vJTAG_inst.v(1) near text “(“; expecting “;”

Error (10839): Verilog HDL error at vJTAG_inst.v(1): declaring global objects is a SystemVerilog feature

How can i fix this?

2)It is possible in some way communicate without quartus_stp.exe but directly with a C# program using VJTag?

3)I have an USB to Serial TTL Module (http://www.aliexpress.com/product-gs/492071325-CP2102-Serial-Converter-USB-2-0-To-TTL-UART-6PIN-Module-OT814-wholesalers.html), is very cheap but is more dangerous use this with two I/O pin instead of VJTAG?

4)What about making post on DE0-Nano pin I/O and how interacting FPGA with an MCU (for example Arduino)? There is not much documentation about LVTTL, etc..

Very good work
Keep posting

Ciao
Leonardo

Thanks for motivating me!

Ciao,
Chris

Ciao

You’re welcome!

I haven’t used any megafunctions with ModelSim yet, so I’m not positive how to get them to work. I’m guessing you’ll need to add the megafunction to the ‘Library’ prior to starting the simulation, similar to how you added the “cycloneive_ver” to the Library…

I’ll take a look when I get a chance, but if you figure it out, please drop by and let us know

Great introduction, has saved me hours, many thanks. Just one question, I have a design that uses a Megafunction and Modelsim complains that it can’t find it. Any suggestions as to how you can simulate when Megafunctions are included.

Thanks

Hammy