Comments for Idle-Logic http://idle-logic.com The Official Blog of Chris Zeh Sat, 28 Jan 2012 22:58:39 +0000 hourly 1 http://wordpress.org/?v=3.3.1 Comment on Installing Quartus II on Ubuntu Lucid by alejo http://idle-logic.com/2010/12/05/installing-quartus-ii-on-ubuntu-lucid/comment-page-1/#comment-213 alejo Sat, 28 Jan 2012 22:58:39 +0000 http://idle-logic.com/?p=795#comment-213 http://thomasreinbacher.wasner.it/techStuff/installQuartusII.txt http://thomasreinbacher.wasner.it/techStuff/installQuartusII.txt

]]> Comment on Using ModelSim with Quartus II and the DE0-Nano by Chris Zeh http://idle-logic.com/2011/12/04/using-modelsim-with-quartus-ii-and-the-de0-nano/comment-page-1/#comment-210 Chris Zeh Mon, 19 Dec 2011 18:18:41 +0000 http://idle-logic.com/?p=1116#comment-210 Glad to hear it. I wish the software had better ways to auto-upgrade, or to notify you automatically of updates. Ah well, some day I'm sure. Glad to hear it. I wish the software had better ways to auto-upgrade, or to notify you automatically of updates. Ah well, some day I’m sure.

]]> Comment on Using ModelSim with Quartus II and the DE0-Nano by Rodrigo http://idle-logic.com/2011/12/04/using-modelsim-with-quartus-ii-and-the-de0-nano/comment-page-1/#comment-208 Rodrigo Sat, 17 Dec 2011 20:35:29 +0000 http://idle-logic.com/?p=1116#comment-208 I just installed QuartusII 11.1sp1 and Modelsim 10.0c starter edition, and the gate-level simulation works perfectly, thanks for the help. I just installed QuartusII 11.1sp1 and Modelsim 10.0c starter edition, and the gate-level simulation works perfectly, thanks for the help.

]]> Comment on Programming the Cyclone II using C++, libftdi and a FT2232H by russdx http://idle-logic.com/2011/03/22/programming-the-cyclone-ii-using-c-libftdi-and-a-ft2232h/comment-page-1/#comment-206 russdx Thu, 15 Dec 2011 10:06:10 +0000 http://idle-logic.com/?p=1027#comment-206 ah, thats very interesting i plan to use this exact chip for one of my projects and i need upto 100k a sec at least, my plan was to use bit bang mode with a nice 8bit bus from the ftdi chip. but if this is all it can do, i think ill just go down the normal uart route hehe :) ah, thats very interesting i plan to use this exact chip for one of my projects and i need upto 100k a sec at least, my plan was to use bit bang mode with a nice 8bit bus from the ftdi chip.

but if this is all it can do, i think ill just go down the normal uart route hehe :)

]]> Comment on Using ModelSim with Quartus II and the DE0-Nano by Chris Zeh http://idle-logic.com/2011/12/04/using-modelsim-with-quartus-ii-and-the-de0-nano/comment-page-1/#comment-205 Chris Zeh Thu, 15 Dec 2011 04:50:56 +0000 http://idle-logic.com/?p=1116#comment-205 No problem. Let me know if you still run into problems after the upgrade. No problem. Let me know if you still run into problems after the upgrade.

]]> Comment on Using ModelSim with Quartus II and the DE0-Nano by Rodrigo http://idle-logic.com/2011/12/04/using-modelsim-with-quartus-ii-and-the-de0-nano/comment-page-1/#comment-204 Rodrigo Wed, 14 Dec 2011 22:38:56 +0000 http://idle-logic.com/?p=1116#comment-204 Hi Chris, you are right, Im using Quartus II 10.1 and ModelSim 6.6c, that must be the problem. I'm going to update de version and see what happen, thanks for the info. Hi Chris, you are right, Im using Quartus II 10.1 and ModelSim 6.6c, that must be the problem. I’m going to update de version and see what happen, thanks for the info.

]]> Comment on Programming the Cyclone II using C++, libftdi and a FT2232H by Chris Zeh http://idle-logic.com/2011/03/22/programming-the-cyclone-ii-using-c-libftdi-and-a-ft2232h/comment-page-1/#comment-202 Chris Zeh Wed, 14 Dec 2011 15:36:40 +0000 http://idle-logic.com/?p=1027#comment-202 Hi Russel, I'm not positive the max throughput for this IC, but I assume that it is quoted for UART mode of operation. Traditionally bit-banging is much slower, and I'm not sure if the drivers are optimized to maximize throughput in this mode. Hi Russel, I’m not positive the max throughput for this IC, but I assume that it is quoted for UART mode of operation. Traditionally bit-banging is much slower, and I’m not sure if the drivers are optimized to maximize throughput in this mode.

]]> Comment on Programming the Cyclone II using C++, libftdi and a FT2232H by russdx http://idle-logic.com/2011/03/22/programming-the-cyclone-ii-using-c-libftdi-and-a-ft2232h/comment-page-1/#comment-201 russdx Wed, 14 Dec 2011 10:34:51 +0000 http://idle-logic.com/?p=1027#comment-201 50k in 3seconds seams VERY slow for this ftdi chip, i thought it was ment to support up to 12mbs? 50k in 3seconds seams VERY slow for this ftdi chip, i thought it was ment to support up to 12mbs?

]]> Comment on Using ModelSim with Quartus II and the DE0-Nano by Chris Zeh http://idle-logic.com/2011/12/04/using-modelsim-with-quartus-ii-and-the-de0-nano/comment-page-1/#comment-200 Chris Zeh Tue, 13 Dec 2011 20:45:29 +0000 http://idle-logic.com/?p=1116#comment-200 Hi Rodrigo, Hopefully I can help. What versions of Quartus and ModelSim are you using? It looks like this might be a problem with the Software version 10.1, but is fixed with the 10.1sp1 software. Sounds like an upgrade might get you all fixed up. Let me know. Hi Rodrigo,

Hopefully I can help. What versions of Quartus and ModelSim are you using? It looks like this might be a problem with the Software version 10.1, but is fixed with the 10.1sp1 software.

Sounds like an upgrade might get you all fixed up.

Let me know.

]]> Comment on Using ModelSim with Quartus II and the DE0-Nano by Rodrigo http://idle-logic.com/2011/12/04/using-modelsim-with-quartus-ii-and-the-de0-nano/comment-page-1/#comment-199 Rodrigo Tue, 13 Dec 2011 15:51:08 +0000 http://idle-logic.com/?p=1116#comment-199 Hello. thank you for the example, it has been very useful for me. but I have a problem when I try to simulate at Gate-Level. this error appears in my transcript chart: # Loading instances from SimpleInverter_6_1200mv_85c_v_slow.sdo # ** Fatal: SDF files require Altera primitive library # Time: 0 ps Iteration: 0 Instance: /SimpleInverter File: SimpleInverter_6_1200mv_85c_slow.vo # FATAL ERROR while loading design # Error loading design Please, can you help me with this. thanks Hello. thank you for the example, it has been very useful for me. but I have a problem when I try to simulate at Gate-Level. this error appears in my transcript chart:

# Loading instances from SimpleInverter_6_1200mv_85c_v_slow.sdo
# ** Fatal: SDF files require Altera primitive library
# Time: 0 ps Iteration: 0 Instance: /SimpleInverter File: SimpleInverter_6_1200mv_85c_slow.vo
# FATAL ERROR while loading design
# Error loading design

Please, can you help me with this. thanks

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